Lately, a low-voltage differential signaling (LVDS) interface is frequently being used for data transmission between a timing controller and data driver ICs of a display device. The LVDS interface is a parallel interface, and a plurality of data diver ICs are connected with a pair of LVDS interfaces. However, a data driver IC having a capacitance load component is connected to one signal line, which causes an impedance mismatch and limits a slew rate. Consequently, a problem occurs in high-speed operation. To solve this problem, a point-to-point interface is used, and a phase-locked loop (PLL) or delay-locked loop (DLL) is used for clock and data recovery. Here, the PLL and DLL use delay-cell-based circuits. Thus, the PLL and DLL are sensitive to temperature and process variation and vulnerable to supply noise, thus having a poor jitter characteristic. Consequently, a PLL having a low-jitter characteristic is necessary to transfer data between a timing controller and data driver ICs at high speed.